1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to silicon carbide metal-oxide-semiconductor field effect transistors (MOSFETs) having self-aligned gate electrodes and a method of fabricating these MOSFETs.
2. Description of the Prior Art
Silicon carbide (SiC) is a crystalline substance that can withstand very high temperatures. Semiconductor devices manufactured on a SiC substrate can withstand temperatures in excess of 200.degree. C. Thus, SiC based semiconductors are desirable for applications that require exposure to high temperatures.
An illustrative high temperature environment is the area near the exhaust of a gas turbine such as employed in an aircraft jet engine. Typically, high temperature sensors are used for monitoring the chemical content of the exhaust gases; however, electronic amplifiers for amplifying the sensor signals must be situated at some distance from the exhaust to avoid performance degradation or destruction on account of the high temperatures near the exhaust. Detrimentally, the signal level from the sensor is attenuated by resistive losses in the connective wiring as the signal propagates from the sensor to a remote amplifier. As a result, the signal-to-noise ratio (SNR) is reduced. Preferably, a sensor and an amplifier should be combined so that very little attenuation of the signal occurs as the signal passes from the sensor to the amplifier. Advantageously, a SiC semiconductor amplifier is capable of withstanding the high temperatures near a turbine exhaust outlet. Therefore, use of a combined SiC based semiconductor amplifier and sensor would result in improved exhaust monitoring apparatus.
Typically, sensor output signals are low level voltages. To amplify low level voltages, a high gain-bandwidth product, high input impedance amplifier is commonly used. Because most types of MOSFETs exhibit a high gain-bandwidth product and high input impedance, they are generally preferred over bipolar transistors for use in sensor signal amplifiers. However, techniques for manufacturing SiC MOSFETs with a sufficient gain-bandwidth product for use in high temperature amplifiers have previously been unavailable.
The theoretical maximum gain-bandwidth product of a typical MOSFET, i.e., neglecting all stray capacitance and resistance, is calculated using equation (1) as follows: ##EQU1## where .mu..sub.c is the effective channel mobility, V.sub.g and V.sub.T are the gate and threshold voltages, respectively, and L is the length of the modulated surface channel. Reasonable values of .mu..sub.c (50 cm.sup.2 /v-sec for p-channel devices and 300 cm.sup.2 /v-sec for n-channel devices), V.sub.g -V.sub.T (approximately 5 volts), and L (approximately 2 microns) yield gain-bandwidth products between 1 and 6 GHz. Inclusion of stray capacitances and parasitic admittances rapidly reduce this figure by an order of magnitude; therefore, MOSFET designs must be tailored to reduce stray capacitance and admittance to achieve performance approaching the ideal.
One design feature of a MOSFET that can be altered to reduce stray capacitance is overlap or misalignment of the gate and drain, or gate and source. Ideally, the gate should not overlap either the drain or the source since any overlap adds to the stray capacitance; however, complete elimination of the overlap is impossible for practical reasons. Nonetheless, use of self-aligning manufacturing techniques, i.e., techniques through which gate edges and drain and source region edges automatically and inherently align as a result of the manufacturing process, can produce MOSFETs having electrical characteristics that approach the ideal.
Manufacturing techniques that create self-aligning gate structures have heretofore been applicable only to the manufacture of silicon based MOSFETs. For example, such MOSFETs have been created using an ion implantation process to selectively bombard a silicon substrate with appropriate ions to produce regions of varying conductivity. Specifically, if the substrate is of p-type conductivity, a combination of a thick silicon dioxide pattern and a gate electrode on a thinner region of the silicon dioxide pattern are used to define those areas of the substrate that are to be implanted with n-type ions to form the source and drain regions of the MOSFET. The ions will penetrate the crystal lattice of the silicon substrate only in the areas which are exposed to the ion beam, i.e., not covered with thick oxide or oxide and gate metal. The portion of the silicon dioxide pattern lying beneath the gate electrode forms an insulating oxide layer for the MOSFET gate. The gate structure, (i.e., gate metal and gate oxide layer) is located between the newly formed source and drain regions.
Subsequent to ion implantation of the drain and source regions, the transistor substrate is heated in a furnace to activate the impurities and anneal the silicon lattice to remove lattice damage caused by the implantation of ions. Since the oxide layer and gate metal pattern were used as the ion implantation mask that defined the location of the drain and source regions prior to their formation, the edges of the gate structure are inherently aligned with the field edges of the source and drain regions without much, if any, overlap.
The alignment of the gate structure with the source and drain regions avoids excess gate-to-source and gate-to-drain capacitance. The low capacitance enables the silicon MOSFETs to operate at higher speeds, i.e., approaching the ideal gain-bandwidth product. Additionally, since the gate mask becomes a functional part of the MOSFET, the self-aligned process reduces the number of processing steps needed in making the transistor.
Unfortunately, the process for producing self-aligned gate structures for silicon MOSFETs is not applicable to silicon carbide MOSFETs, primarily owing to the need to anneal the substrate after it has been ion implanted. The annealing temperature for silicon carbide is so high (i.e., on the order of 1200.degree. C. or higher) as to destroy the oxide layer mask and produce defects in the gate oxide beneath the gate electrode. Since, for the most part, the oxide mask is no longer present and the gate may be short-circuited to the channel region, the advantages of self-alignment are effectively unrealized. Corrective measures, such as attempting to redeposit or reform the oxide layer and gate electrode, require application of a gate electrode mask. Due to inaccuracies in mask alignment during the reformation process, corrective reformation of the gate structure is not effective at creating an aligned gate electrode. For example, limitations in manufacturing accuracy can result in an approximately 2.5.mu. uncertainty in alignment of a single mask over an existing pattern. Thus an overlap of up to 2.5.mu. between the gate and drain or source can result.
Given the ineffectiveness of using an ion implantation technique to form an aligned gate structure in SiC MOSFETs, manufacturers have employed an epitaxy process to form nonaligned gate structures. The epitaxy process for generating a nonaligned gate structure requires use of a mask to pattern a layer of metal into the gate electrode. As with the ion implantation process, the mask alignment error can be as much as 2.5.mu.; however, the extra processing step needed to reform a damaged gate produced by the ion implantation process is not necessary with epitaxy fabrication. Therefore, the epitaxy process is generally preferred over ion implantation for manufacturing SiC MOSFETs.
Thus, a need exists for SiC MOSFETs having aligned gate structures and for a method of manufacture that relies on an epitaxial process but enables SiC MOSFETs to be produced with aligned gate structures. Preferably, the gate structure should be self-aligning in the MOSFET manufacturing process.